On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
نویسنده
چکیده
Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a nonnegligible way, for chips with or without fault-tolerance.
منابع مشابه
On the effect of floorplanning on the yield of large area integrated circuits
{ Until recently, VLSI designers rarely considered yield issues when selecting a oorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the oorplan can aaect the projected yield. We study several general oorplan structures, make some speciic recommendations, and apply them to actual VLSI chips...
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